This course includes:
This course consists of commonly asked Verilog questions, core Verilog concepts, and Coding styles required to ace Technical rounds. This course will also help you quickly revise core Verilog concepts frequently tested in the FPGA / VLSI / ASIC Interviews before appearing for Interviews. Course will not discuss the fundamentals of Verilog in detail as the focus of the course is to cover all the must-know Verilog concepts within a day before appearing for the interview.
Who this course is for:
15 sections - 54 lectures - 01:27:16 total length
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I am working as FPGA Developer at Edelweiss for the development of a High-Frequency Trading platform on Xilinx Alveo Cards. Before Joining Edelweiss, I was VLSI Trainer at Sardar Patel Institute of Technology. I also worked as Research Scientist at Society for Applied Microwave Electronics Engineering & Research(SAMEER) in the development of the Gradient Control System for Indigenous Magnetic Resonance Imaging. I being a consultant with the Larsen & Toubro Technology Services, Power International in the development of various FPGA based Systems such as Simultaneous DAQ, Multi-channel Logic Analyzers, and DTS. My area of interest includes Front End VLSI Design, SoC, and Chip Verification.